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    1. Parasitic Capacitance Analytical Model for Sub-7-nm Multigate Devices

      by Martinie, S.; Jaud, M.-A; Barraud, S.; Lacord, J.; Barbe, J. C. and Rozeau, O.

      Ieee Transactions On Electron Devices, Volume 63, Issue 2, pp. 781 - 786

      Journal Article : Full Text Online

    2. Impact of Equivalent Oxide Thickness on Threshold Voltage Variation Induced by Work-Function (...)

      by Youngtaek Lee and Changhwan Shin

      Ieee Transactions On Electron Devices, Volume 64, Issue 5, pp. 2452 - 2456

      Journal Article : Full Text Online

    3. 3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits

      by Jha, Niraj K.; Bhoj, Ajay N. and Joshi, Rajiv V.

      Ieee Transactions On Very Large Scale Integration (Vlsi) Systems, Volume 21, Issue 11, pp. 2094 - 2105

      Journal Article : Full Text Online

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    1. High-k Materials in Multi-Gate FET Devices

      edited by Shubham Tayal, Parveen Singla, and J. Paulo Davim.

      Book : View Online

    2. Multigate transistors for high frequency applications

      K. Sivasankaran and Partha Sharathi Mallick.

      Book : View Online

    3. Variation aware analog and mixed-signal circuit design in emerging multi-gate CMOS technologies

      Michael Fulde.

      Book : View Online

    See all 22 Books & Media results

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